The present invention is directed to improved means and methods for handling errors detected when transferring data in a data processing system, and more particularly when employed in connection with the reading and writing of data in a random access memory of the type disclosed in the cross-referenced applications.
Random access memories are well known in the computer art. Such memories can be constructed from many different types of bit storing devices, such as magnetic and semiconductor elements and the like. By random access is meant that the elements are grouped together into locations and that data items can be written into or read from any group of elements or cells forming one location in approximately the same time as from any other location.
In early computer systems the data to be processed was usually grouped into words having a field length equal to the number of elements or cells per location in the system memory. As the range of problems presented to data processing systems expanded, the types of formats used to represent data items have multiplied. Thus, the memory has been required to store fields of data which may have variable field lengths shorter than or longer than the number of cells in a location. Also, in order to use the available storage capacity of the memory efficiently, it has become necessary to be able to specify not only a specific location in the memory, but also to specify particular cells within a selected memory location.
In the cross-referenced U.S. Pat. No. 3,781,812, an advantageous memory addressing system is disclosed which provides variable field length and bit addressing capabilities, and also permits memory cells to be accessed on either side of a designated boundary. A bit addressable, variable field memory system of the type disclosed in this patent is currently employed in Burroughs B 1700 computer systems.
In the preferred embodiment disclosed in the cross-referenced Pat. No. 3,781,812, the memory is partitioned into a plurality of independently operating modules. Fields of data bits can be stored in one or more modules, that is, partly in one module and partly in other modules. Each module is coupled to its own access control circuitry and, during a particular access operation, data is simultaneously transferred in parallel to or from one or more modules as determined by field length and direction indicating portions of the applied addressing information. Rotation and masking circuitry responsive to starting bit and field length information serve to rotate and mask the transferred data so that it is compatible with the memory and processor formats being employed and so that unwanted data outside of the desired field is inhibited.